Dsp processor architecture mcq questions

One of the biggest bottlenecks in executing DSP algorithms is transferring information to and from memory. This includes datasuch as samples from the input signal and the filter coefficients, as well as program instructionsthe binary codes that go into the program sequencer.

For example, suppose we need to multiply two numbers that reside somewhere in memory. To do this, we must fetch three binary values from memory, the numbers to be multiplied, plus the program instruction describing what to do.

Figure a shows how this seemingly simple task is done in a traditional microprocessor. This is often called a Von Neumann architectureafter the brilliant American mathematician John Von Neumann Von Neumann guided the mathematics of many important discoveries of the early twentieth century.

His many achievements include: developing the concept of a stored program computer, formalizing the mathematics of quantum mechanics, and work on the atomic bomb. If it was new and exciting, Von Neumann was there! As shown in aa Von Neumann architecture contains a single memory and a single bus for transferring data into and out of the central processing unit CPU. Multiplying two numbers requires at least three clock cycles, one to transfer each of the three numbers over the bus from the memory to the CPU.

We don't count the time to transfer the result back to memory, because we assume that it remains in the CPU for additional manipulation such as the sum of products in an FIR filter. The Von Neumann design is quite satisfactory when you are content to execute all of the required tasks in serial. In fact, most computers today are of the Von Neumann design. We only need other architectures when very fast processing is required, and we are willing to pay the price of increased complexity.

This leads us to the Harvard architectureshown in b. This is named for the work done at Harvard University in the s under the leadership of Howard Aiken As shown in this illustration, Aiken insisted on separate memories for data and program instructions, with separate buses for each. Since the buses operate independently, program instructions and data can be fetched at the same time, improving the speed over the single bus design.

Most present day DSPs use this dual bus architecture. Figure c illustrates the next level of sophistication, the Super Harvard Architecture. The idea is to build upon the Harvard architecture by adding features to improve the throughput.

First, let's look at how the instruction cache improves the performance of the Harvard architecture. A handicap of the basic Harvard design is that the data memory bus is busier than the program memory bus.Part 1: List for questions and answers of Digital Signal Processing. Slaughter numerical paper but it also consists of some very important theory portions that are required to be The questions are accompanied with reasons and solutions. Digital Signal Processing is an important branch of Electronics and Telecommunication engineering that deals with the improvisation of reliability and accuracy of the digital communication by employing multiple techniques.

Direction for questions 63 to Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3. The ROM programmed during manufacturing process itself is called - Output of the assembler in machine codes is referred to as - The software used to drive microprocessor-based systems is called. The software used to drive microprocessor-based systems is called assembly language. If yes then you can take up a Digital Signal Processing job to improve the accuracy of communication in this digital world.

DSP unit — 5 Download here. Learn how your comment data is processed. On our wisdomjobs page, we share with you information of the skills required, training courses available and various job opportunities related to the Digital Signal Processing job.

This set of MCQ on multiprocessor and real-time scheduling includes collections on top 20 multiple-choice questions on the proposals for multiprocessor thread scheduling. Advantages of DSP are: a. Sharing a single processor among a number of signals by time sharing This section focuses on "Processing" in XML.

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In DSP processors, which among the following maintains the track of addresses of input data as well as the coefficients stored in data and program memories? Multiple choice questions and answers MCQ based on the Procedures and Macros of the microprocessor with 4 choices, correct answer and explanation. MCQ Quiz on Microprocessor and Microcontroller Multiple Choice Questions and Answers on microprocessor and microcontroller objective question and answer to prepare students to learn and grow their skill and knowledge in microprocessor and microcontroller quiz test pdf question in development and prepare for interviews and various competitive exams.

C - Arrays and Pointers. DSP processors are featured to support high performance and repeatitive and intensive tasks whereas microprocessors are not application specific and they are designed to process control-oriented tasks.

Which of the following are the proposals for multiprocessor thread scheduling and processor assignment? Email us [email protected] We love to get feedback and we will do our best to make you happy. By signing up, you are agreeing to our terms of use.

These short solved questions or quizzes are provided by Gkseries. Are you interested in Digital Communications? Here you will find a list of common important questions on basic computer knowledge in MCQ quiz style with answer for competitive exams and interviews.

Memory devices. State the name of software used to pefrorm DSP Practicals? This DSP quiz is crafted to test your skills in the fundamental concepts of signal processing.A refers to a computer system capable of processing several programs at the same time.

B represents organization of single computer containing a control unit, processor unit and a memory unit. C includes many processing units under the supervision of a common control unit D none of the above. Ans: C. Suppose that a bus has 16 data lines and requires 4 cycles of nsecs each to transfer data.

If the cycle time of the bus was reduced to nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus? Assembly language A uses alphabetic codes in place of binary numbers used in machine language B is the easiest language to write programs C need not be translated into machine language D None of these Ans: A. The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time.

Rotational latency refers to A the time its takes for the platter to make a full rotation B the time it takes for the read-write head to move into position over the appropriate track C the time it takes for the platter to rotate the correct sector under the head D none of the above Ans: A.

What characteristic of RAM memory makes it not suitable for permanent storage? A giving programming versatility to the user by providing facilities as pointers to memory counters for loop control B to reduce no. The average time required to reach a storage location in memory and obtain its contents is called the A seek time B turnaround time C access time D transfer time Ans: C. Which of the following is not a weighted code? The idea of cache memory is based A on the property of locality of reference B on the heuristic rule C on the fact that references generally tend to cluster D all of the above Ans: A.

Which of the following is lowest in memory hierarchy? In a vectored interrupt. A the branch address is assigned to a fixed location in memory.

B the interrupting source supplies the branch information to the processor through an interrupt vector. C the branch address is obtained from a register in the processor D none of the above Ans: B. In signed-magnitude binary division, if the dividend is 2 and divisor is 2 then the result is A 2 B 2 C 2 D 2 Ans: B. In a program using subroutine call instruction, it is necessary A initialise program counter B Clear the accumulator C Reset the microprocessor D Clear the instruction register Ans: D.

If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Ans: D. B Registers which keep track of when the program was last accessed. C Counters to keep track of last accessed instruction.Two byte B.

dsp processor architecture mcq questions

Four Byte C. Eight Byte D. Six Byte. Which of the following is False? The ability to store data in the form of consecutive bytes. These ARM processors are designed for handheld devices. ARM is a type of system architecture. Both A and B. Simple Address B. Complex Address C. Non-Effective address D. Effective address. View Answer Ans : D Explanation: Effective address is the address that the computer acquires from the current instruction being executed.

Banked switching B. Extential switching C. Internal switching. View Answer Ans : C Explanation: The duplicate registers are used in situations of context switching. Which instruction is used to list the registers used for execution? Which instruction is basically used to check the branch enable bit?

BEQ B. Which of the following is true? The LDM instruction is used to load data into multiple locations. The MLA instruction is used perform addition and multiplication together. All of the above. Ans : A Explanation: Option A is false. Ans : D Explanation: Effective address is the address that the computer acquires from the current instruction being executed. Ans : C Explanation: The duplicate registers are used in situations of context switching. Ans : B Explanation: This instruction is used to list the registers used for execution.

Ans : D Explanation: All statement are correct. Ans : C Explanation: The offset is used to get the new branching address of the process.D worksM. Tech and B. TechSchool Projects, Please send email : ijisea org. Please click the Below link to download this material.

Model paper - 1. Model Paper In the Frequency Transformations of the analog domain the transformation is a. Low Pass to Lowpass. Lowpass to Highpass. Lowpass to Bandpass. Lowpass to Bandreject. The magnitude response of the following filter decreases monotonically as frequency increases. Butterworth Filter. Chebyshev type - 1. Chebyshev type - 2. FIR Filter. The transition band is more in. The poles of Butterworth filter lies on.

I I R digital filters are of the following nature. Non Recursive. Non Reversive. In I I R digital filter the present output depends on. Present and previous Inputs only. Present input and previous outputs only. Present input only. Present Input, Previous input and output. Lower sidelobes in stopband. Higher Sidelobes in stopband. Lower sidelobes in Passband.

No sidelobes in stopband. In the case of I I R filter which of the following is true if the phase distortion is tolerable. More parameters for design. More memory requirement.


Lower computational Complexity.What does the control unit generate to control other units? Transfer signals B. Command Signals C. Control signals D. Timing signals. Answer - Click Here: D. Unconditional transfer B.

Controlled transfer C. Conditional transfer D.

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None of these. Answer - Click Here: A. Stored Values B.

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Information C. Data D. Answer - Click Here: C. Any instruction initiates interrupt which are: A. Answer - Click Here: B.

dsp processor architecture mcq questions

When does the input devices send information to the processor? When the data arrives regardless of the SIN flag B. When the SIN status flag is set C.

Either of the cases D.Skip to content. Please wait while the activity loads. If this activity does not load, try refreshing your browser. Also, this page requires javascript. Please visit using a browser with javascript enabled. If loading fails, click here to try again. Question 1. Which of the following addressing modes are suitable for program relocation at run time?

Question 1 Explanation:. Explanation: Program relocation at run time transfer complete block to some memory locations. This requires as base address and block should be relatively addressed through this base address. This require both base address and relative address. Absolute addressing mode and indirect addressing modes is used for one instruction at one time, not for whole block So both are not suitable for program relocation at run time.

Question 2. Direction for questions 63 to Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

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If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address in decimal saved in the stack will be. Question 2 Explanation:.

dsp processor architecture mcq questions

Instructions size are given in words. So first instruction will take 2 words i.

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As 1st instruction starts from and the size is 8 bytes second instruction address will belike wise 3rd instruction address will be ,4th instruction address ,5th instruction address and halt instruction address will be As an interrupt occurs executing the HALT instruction, the return address in decimal saved in the stack will be the address of the halt instruction. Question 3. Directions for question 63 to Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

Question 3 Explanation:.

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The clock cycles are per block; if an instruction size is 2 then it requires twice no. Instruction no. Question 4. The microinstructions stored in the control memory of a processor have a width of 26 bits.

Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field Xand a MUX select field Y.

There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words? Question 4 Explanation:. MUX has 8 states bits as input lines so we require 3 select inputs to select and input lines.

Dsp processor architecture mcq questions

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